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Additional resources for 64.VLSI Systems
Variations of this magnitude are quite common in modern semiconductor technologies. This topic is of immediate importance to the existing high-speed processor community.
1,11,35,52,59,61,62). ’’ In each of these clock distribution networks, significant effort has been placed on accurately estimating the magnitude of the resistive and capacitive interconnect impedances to determine the effect of these RC loads on the shape of the clock signal waveform. This information is typically back annotated into a SPICE-like circuit simulator to adjust the clock delays for minimum clock skew (63). Minimal work exists, however, in developing circuit procedures and algorithms for automating the circuit design of clock distribution networks in structured custom VLSI circuits (64–67).
However, in most large VLSI circuits, the physical distances are such that line resistances coupled with any via/contact resistances and the significant line and coupling capacitances will create large interconnect impedances. Therefore, even with a centrally located clock generation and distribution circuit, additional techniques are required to compensate for variations in interconnect and register loading. , the number and load of the clocked registers per clock signal path). Clock buffers are placed along the clock path such that the highly resistive interconnect lines (typically long lines) drive loads with low capacitance, whereas the low-resistance interconnect lines (typically short lines) drive loads with high capacitance.